1. Field of the Invention
This invention relates to communication switching.
2. Related Art
In switching in communication networks, one important feature is speed. It is generally desirable for switches in such networks to operate as quickly and with as little latency as possible. One method by which switches are known to operate quickly is to synchronously switch individual cells of messages; thus, each cell to be switched is the same length and the switch operates at the start of each cell time to transfer cells from assigned input queues to assigned output queues.
One problem in the known art is that, for the switch to operate on parallel data, it will require a very large number of incoming and outgoing communication paths for individual message bits. However, if the switch is at all sizable, this makes connectivity with the switch, and the switch backplane itself, extremely unwieldy and expensive. For example, to support 16 input queues and 16 output queues each operating at 3.2 gigabits per second, each interface to the interconnect would require a 64 bit bus operating at 50 MHz, totaling 2048 connectors for data alone. Control signal connectors and power connectors would add to this total.
Alternatively, for the switch to operate on serial data, the receiving output queues must recover clock signals from the data signals and synchronize to the transmitted clock signals as they are received. Synchronization to transmitted clock signals can be performed with a phase-locked loop (PLL). However, if the switch is at all rapid, the time required to synchronize will be a substantial fraction of the cell time for switching, and thus substantially increase the time overhead for switching.
Accordingly, it would be desirable to provide a method and system for rapidly synchronously switching large amounts of data, particularly in a cell-based switch. This advantage is achieved in an embodiment of the invention in which the switch interconnect operates asynchronously and serially, but appears to operate synchronously, by using a single clock signal source which is uniform for the switch interconnect and its input and output queues and thus accrues no synchronization delay.